Towards Run-Time Re-Configurable Techniques for Real-Time Embedded Applications

Many embedded applications can benefit from the flexible custom computing opportunities that FPGA technology offers. The Run-Time Reconfiguration (RTR) of the FPGA as an application is being served provides further flexibility. It gives the opportunity to reuse FPGA space used by custom computing circuits that are not operational in a given time frame. Custom computing circuits can meet very tight real-time requirements but when it comes to reconfiguring these circuits, the time taken can be comparatively long and non-deterministic. There is a need for a suitable development environment to investigate how to cope with or reduce the RTR time. This paper describes how this can be achieved with currently available tools and technologies. We first review an appropriate subset of the available technology to implement a system comprising a CPU running a RTOS on a SoPC that can ébe adapted using RTR. Then we propose a system architecture that is feasible with current technology. We outline the processes and databases needed to support RTR of the SoPC. We present how the RTOS is made aware of the architectural constraints and reconfiguration options, thus simplifying the use of reconfigurable hardware for the application programmer.